1. Field of the Invention
The present invention relates to integrated circuits and more particularly to the protection of integrated circuits against electrostatic discharge (ESD—ElectroStatic Discharge).
One embodiment of the present invention applies mainly, but not exclusively, to CMOS-type (Complementary Metal-Oxide Semiconductor) integrated circuit technologies.
2. Description of the Related Art
One of the major problems of the reliability of integrated circuits relates to faults due to electrostatic discharge (ESD). This type of fault represents a critical problem in modern technologies as a result of the increasing miniaturization of integrated circuits. Indeed, reducing the dimensions of integrated circuits and therefore the distances between the elements increases the predominance of parasitic elements that can trigger themselves more rapidly and at voltages that tend towards the nominal operating voltage.
When an electrostatic discharge occurs on a contact pad of an integrated circuit, a high positive or negative voltage of several thousands of Volts compared to the ground can appear on the contact pad.
FIG. 1 represents a contact pad connected to an electric circuit forming an output or input/output port (buffer) of a CMOS-type integrated circuit. The port comprises a P-channel MOS transistor MP1 and an N-channel MOS transistor MN1 the gate of which is controlled by a control signal Cntl. The source of the transistor MP1 is connected to a supply terminal Vdd, and the drain of this transistor is connected to the drain of the transistor MN1 and to an output terminal Pad that must be protected of the output port. The source of the transistor MN1 is grounded.
FIG. 2 represents in a cross-section the transistor MN1 formed in a substrate of a P-doped semiconductor material 1 of an integrated circuit IC. The transistor MN1 comprises two N+-doped regions 5, 11 forming the drain and the source of the transistor, and a polysilicon gate 8 formed on the substrate between the regions 5 and 11. The output port comprises a contact pad 6 formed on the region 5 to connect the output of the output port to an output terminal Pad. The output port comprises a control terminal Cntl connected to a contact pad 9 formed on the gate 8. A ground connection contact pad 12 is formed on the region 11. The integrated circuit also comprises two P+-doped regions 3, 13, formed in the substrate 1 on either side of the regions 5, 11. Contact pads 4, 14 are formed on the regions 3, 13 to connect the integrated circuit to the ground.
The doped regions 5 and 11 form with the substrate a parasitic bipolar transistor T1 of npn type. The region 5 forms with the substrate a collector—base junction of the transistor T1, and the region 11 forms with the substrate an emitter—base junction of the transistor T1. The base of the transistor T1 is linked to the region 13 through the substrate 1 having a resistance Rsub.
FIG. 3 represents the evolution of the collector—base current of the transistor T1 according to the voltage applied to the terminal Pad, when a positive electrostatic discharge is applied to the connection terminal Pad. The voltage applied to the terminal Pad increases to reach a trigger threshold voltage Vtr. While the voltage increases, the current also increases to reach approximately 1 mA. As soon as the voltage exceeds the trigger voltage Vtr at a point DB, the voltage drops to a minimum voltage Vh, while the current continues to increase. From the point DB, the diode D1 at the drain—substrate junction of the transistor MN1 avalanches. When the minimum voltage Vh is reached, the parasitic transistor T1 is triggered. The result is that the voltage increases again while the current continues to increase more rapidly. From a point F, the voltage drops revealing that the transistor T1 is avalanching.
To limit the appearance or the destructive effects of these discharges, a protection device of the input/output or output ports is integrated into the semiconductor material of the integrated circuit.
Such a protection device is represented in FIG. 4. This device comprises a diode D2 having a minimum resistivity, connected between the drain and the source of the transistor MP1, and a centralized protection circuit ESD1 connected between the supply terminals Vdd and Gnd. In the event that an electrostatic discharge appears on the terminal Pad, the discharge current follows a discharge path DP towards the ground, passing through the diode D2 and the circuit ESD1. For this purpose, the circuit ESD1 is designed to react to a voltage drop more rapidly than the components of the port. It will be understood that the circuit ESD1 must be designed to absorb the discharge current.
In certain applications, it may be impossible to connect a diode between the drain and the source of the transistor MP1. This is the case for example when a bus is shared by several integrated circuits, and when one of the integrated circuits must be switched off for reasons of power consumption, without disturbing the communications on the bus.
A classic protection solution shown in FIG. 5 involves connecting a protection circuit ESD2 between the drain and the source of the transistor MN1. Two essential notions are then to be considered. The first notion is the efficiency of the protection, i.e., the capacity of the protection circuit ESD2 to trigger itself before the parasitic elements of the output port, failing which the output port might be damaged. Indeed, in an open-drain configuration, it can generally be observed that the protection circuit ESD2 competes with the parasitic bipolar transistor T1. The second notion is the robustness of the protection, i.e., the capacity of the protection circuit to absorb the discharge without being damaged.
Concerning the efficiency of the protection, it is possible to improve the trigger characteristics of the protection. This improvement generally leads to increasing the trigger threshold voltage of the parasitic transistor. However, this improvement can affect the robustness of the protection circuit and deteriorate the performances of the output port.
Generally speaking, the spurious phenomena are not modeled, or well known. These phenomena vary particularly according to the manufacturing chain. The result is that nothing guarantees that a protection solution is always efficient if a manufacturing or manufacturing chain parameter is changed. In addition, the increasing miniaturization of integrated circuits tends to increase the efficiency of the parasitic bipolar transistor, to the detriment of the efficiency of the parallel protection circuit. The solutions currently implemented therefore generally have a high cost in terms of overall dimensions, and of influence on the entire architecture of the integrated circuit. These solutions also limit the reduction of the supply voltage of the output port and thus of the thickness of the oxide layers, or require the addition of cascode-arranged transistors to limit the efficiency of the parasitic transistor.
It must be added that a protection can become totally inefficient as a result of the fact that the stress caused by the discharge tends to render the gate of the transistor MN1 floating and therefore to totally change the behavior of the parasitic transistor.